## Step-by-Step Solution ### **1. Understanding the Requirements** - **Target Memory Array:** 128K (16K x 8 bits) - **EEPROM Used:** AT28C64 #### **AT28C64 Specs** - Organization: 8K x 8 bits (64 Kbits) - Address Lines: 13 (A–A12) - Data Lines: 8 (D–D7) #### **Required Memory** - **16K x 8 bits** = 16,384 bytes (per chip) - **128K bytes** = 131,072 bytes - **Number of 8K x 8 chips to get 128K:** \[ \frac{128K}{8K} = 16 \text{ chips} \] --- ### **2. Schematic Structure** #### **a. Memory Expansion** - Each AT28C64 has 8K (8,192) locations. - Need 16 chips to make up 128K. #### **b. Address Lines** - 128K bytes need 17 address lines (since \(2^{17} = 131,072\)) - AT28C64 uses only 13 address lines (A–A12). - The remaining 4 address lines (A13–A16) will select which EEPROM chip is active. #### **c. Chip Select (CS) Logic** - Use a **4-to-16 decoder** (e.g., 74LS154) for A13–A16 to select one out of 16 EEPROMs. --- ### **3. Schematic Block Diagram** ``` Address Bus: A–A16 (Total 17 lines) Data Bus: D–D7 (8-bit bus) ``` #### **Connection Overview** - **A–A12** → All EEPROMs (in parallel) - **A13–A16** → 4-to-16 Decoder Inputs - **Decoder Outputs** → CS (Chip Select) of each AT28C64 - **D–D7** → All EEPROMs (in parallel) --- ### **4. Schematic Diagram** ```plaintext Address Bus (A - A16) | +------------------------------+ | | | | | | | | A-A12 A13-A16 Data Bus (D-D7) | | | | | v | v +----------------+ | +-------| 4-to-16 Decoder|---+---+---+---+---+---+---+---+ | | +----------------+ | | | | | | | | | | (To CS pins of each EEPROM) | | | +---> To select one of 16 EEPROMs | v +-------------------+ +-------------------+ ... +-------------------+ | AT28C64 #1 | | AT28C64 #2 | ... | AT28C64 #16 | | A-A12 <--------|---|<-------- A-A12 | ... |<-------- A-A12 | | D-D7 <------->|---|<-------> D-D7 | ... |<-------> D-D7 | | CS <--------| |<-------- Decoder | ... |<-------- Decoder | +-------------------+ +-------------------+ ... +-------------------+ ``` **Alt text:** Schematic showing 16 AT28C64 EEPROMs with A–A12 parallel, D–D7 parallel, and chip selects from a 4-to-16 decoder fed by A13–A16. --- ### **5. Summary Table** | Feature | Value | |----------------------|--------------------| | Target memory | 128K (16K x 8) | | EEPROM type | AT28C64 (8K x 8) | | Number of EEPROMs | 16 | | Decoder needed | 4-to-16 (for CS) | | Address lines needed | 17 (A–A16) | --- ## **Conclusion** - **Use 16 AT28C64 chips**. - **Use a 4-to-16 decoder** for chip selection. - **Connect address and data lines in parallel** as described. - **Schematic details given above**. If you need a hand-drawn or software-drawn schematic, let me know!