5
.
Suppose the CMOS inverter below drives a
1
5
0
0
um length of n
-
type polysilicon interconnect with the cross section shown below
(
Resistivity for n
-
poly Si is
0
.
0
1
ohm
-
cm
)
.

Question

5
.
 ﻿Suppose the CMOS inverter below drives a 
1
5
0
0
 ﻿um length of n
-
type polysilicon interconnect with the cross section shown below 
(
Resistivity for n
-
poly Si is 
0
.
0
1
 ﻿ohm
-
cm
)
.
 
(
4
0
 ﻿pts
)
 ﻿Vop 
=
 
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.
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V gate dimensions in um Vrx 
=
 
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=
 
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.
6
V Mpo tox 
=
 
8
 ﻿nm Lov 
=
 
0
.
0
2
 ﻿pm 
1
.
0
/
 
0
2
 
로
 ﻿IN OUT 
1
5
0
0
 ﻿um n
-
poly interconnect Mio 
0
4
0
2
 ﻿n
-
type polysilicon 
0
4
 ﻿jum 
0
.
6
 ﻿um 
0
.
4
m silicon dioxide Si substrate 
(
a
)
 ﻿Find the resistance per unit length and capacitance per unit length for the interconnect 
(
b
)
 ﻿Estimate the tph of the driving gate based on the total capacitance of the interconnect. 
(
c
)
 ﻿Using the results above, determine which model is most appropriate for the interconnect: the lumped capacitance model or the distributed rc model?

VIPSolutions · Accepted Answer

# CMOS Inverter Driving n-Polysilicon Interconnect

## Given Data

- **Interconnect length ($L$)**: 150 μm = .15 cm  
- **Interconnect cross-section**: width ($w$) = .4 μm, thickness ($t$) = .6 μm  
- **Resistivity ($\rho$)**: .01 Ω·cm (for n-type polysilicon)  
- **SiO₂ thickness ($d_{ox}$)**: .04 μm = 40 nm = .004 cm  
- **Capacitance is between poly and substrate**  
- **Permittivity of SiO₂ ($\epsilon_{ox}$)**: $3.45 \times 10^{-13}$ F/cm  
- **Gate's input capacitance and output resistance not directly given**  
- **Supply voltage**: 2.5 V (for context)

---

## (a) Resistance and Capacitance Per Unit Length

### **Resistance per Unit Length ($R'$)**

$$
R' = \frac{\rho}{A}
$$
Where $A = w \times t$ is the cross-sectional area.

- $w = .4~\mu\text{m} = .4 \times 10^{-4}~\text{cm}$
- $t = .6~\mu\text{m} = .6 \times 10^{-4}~\text{cm}$
- $A = .4 \times .6 \times 10^{-8} = .24 \times 10^{-8}~\text{cm}^2$

$$
R' = \frac{.01~\Omega\cdot\text{cm}}{.24 \times 10^{-8}~\text{cm}^2}
= \frac{.01}{.24} \times 10^8~\Omega/\text{cm}
= .0417 \times 10^8~\Omega/\text{cm}
= 4.17 \times 10^6~\Omega/\text{cm}
= 41.7~\Omega/\mu\text{m}
$$

**Final Value:**
$$
\boxed{R' = 41.7~\Omega/\mu\text{m}}
$$

---

### **Capacitance per Unit Length ($C'$)**

Parallel plate capacitance per unit length:
$$
C' = \epsilon_{ox} \cdot \frac{w}{d_{ox}}
$$

- $\epsilon_{ox} = 3.45 \times 10^{-13}~\text{F/cm}$
- $w = .4~\mu\text{m} = .4 \times 10^{-4}~\text{cm}$
- $d_{ox} = .04~\mu\text{m} = .04 \times 10^{-4}~\text{cm}$

$$
C' = 3.45 \times 10^{-13} \cdot \frac{.4}{.04}
= 3.45 \times 10^{-13} \cdot 10
= 3.45 \times 10^{-12}~\text{F/cm}
$$

Convert to F/μm:

$$
3.45 \times 10^{-12}~\text{F/cm} \div 10^4 = 3.45 \times 10^{-16}~\text{F}/\mu\text{m}
$$

**Final Value:**
$$
\boxed{C' = 3.45 \times 10^{-16}~\text{F}/\mu\text{m}}
$$

---

## (b) Estimate $ t_{PHL} $ of the Driving Gate

The propagation delay is dominated by the RC delay:

Total resistance:
$$
R_{total} = R' \cdot L = 41.7~\Omega/\mu\text{m} \cdot 150~\mu\text{m} = 62,550~\Omega
$$

Total capacitance:
$$
C_{total} = C' \cdot L = 3.45 \times 10^{-16}~\text{F}/\mu\text{m} \cdot 150~\mu\text{m} = 5.175 \times 10^{-13}~\text{F}
$$

For long interconnects, use the distributed RC delay (Elmore delay):

$$
t_{PHL} \approx .69 \cdot R_{total} \cdot C_{total}
$$
or, for distributed RC line:
$$
t_{PHL} = .38 \cdot R_{total} \cdot C_{total}
$$
But the maximum $ t_{PHL} $ for distributed RC line is:
$$
t_{PHL} \approx .69 \cdot \frac{R_{total} C_{total}}{2}
$$

Let’s calculate both:

$$
R_{total} = 62,550~\Omega
$$
$$
C_{total} = 5.175 \times 10^{-13}~\text{F}
$$

- Lumped RC: $t_{PHL} = .69 \cdot R_{total} \cdot C_{total} = .69 \cdot 62,550 \cdot 5.175 \times 10^{-13}$
- Distributed RC: $t_{PHL} \approx .35 \cdot R_{total} \cdot C_{total}$

$$
t_{PHL, \text{lumped}} = .69 \cdot 62,550 \cdot 5.175 \times 10^{-13}
= .69 \cdot 323,253.75 \times 10^{-13}
= 223,045.09 \times 10^{-13}
= 2.23 \times 10^{-8}~\text{s}
= 22.3~\text{ns}
$$

$$
t_{PHL, \text{distributed}} = .35 \cdot 62,550 \cdot 5.175 \times 10^{-13}
= .35 \cdot 323,253.75 \times 10^{-13}
= 113,138.8 \times 10^{-13}
= 1.13 \times 10^{-8}~\text{s}
= 11.3~\text{ns}
$$

**Estimated propagation delay:**
$$
\boxed{t_{PHL} \approx 11~\text{ns}~(\text{distributed RC model})}
$$

---

## (c) Appropriate Interconnect Model

### **Lumped Capacitance vs. Distributed RC**

- **Lumped capacitance model** is valid when the driver resistance is much greater than the wire resistance ($R_{driver} \gg R_{wire}$).
- **Distributed RC model** is needed when the wire resistance is significant compared to the driver resistance.

#### In this case:
- The interconnect resistance ($62~k\Omega$) is very large (much larger than typical driver output resistance, which is often a few hundred ohms or less).
- The interconnect delay is dominated by the wire's own RC time constant.

**Conclusion:**

$$
\boxed{\text{The distributed RC model is appropriate for this interconnect.}}
$$

---

## **Summary Table**

| Parameter                         | Value                          |
|------------------------------------|-------------------------------|
| Resistance per unit length ($R'$)    | $41.7~\Omega/\mu\text{m}$      |
| Capacitance per unit length ($C'$)   | $3.45 \times 10^{-16}~\text{F}/\mu\text{m}$ |
| Total Resistance ($R_{total}$)       | $62.6~k\Omega$               |
| Total Capacitance ($C_{total}$)      | $517~\text{fF}$              |
| Estimated delay ($t_{PHL}$)         | $11~\text{ns}$               |
| Best interconnect model           | Distributed RC                |

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