Let's solve the problems step by step: --- ### **Question 21** #### **Given:** - Relative mobility (μn/μp) = 2 - Gate schematic as shown - Find the logical effort for input **a** when the output is **falling**. #### **Step 1: Identify NMOS and PMOS** - The **pull-down** network (bottom) uses NMOS transistors (labeled 3, width = 3). - The **pull-up** network (top) uses PMOS transistors (labeled 6, width = 6). #### **Step 2: Find the Equivalent Resistance for Input "a"** When **output is falling**, the NMOS network is responsible for pulling the output to ground. - For input "a", both NMOS transistors are in **series** (both must be ON for output to fall). - Each NMOS has a width of 3, so their resistance is **R/3** each (since resistance ∝ 1/width). Total resistance (series): \[ R_{eq, NMOS} = \frac{R}{3} + \frac{R}{3} = \frac{2R}{3} \] #### **Step 3: Reference Inverter (Effort Calculation)** For a **reference inverter**: - PMOS width = 2 (to match mobility, so resistance is R/2) - NMOS width = 1 (resistance is R) #### **Step 4: Logical Effort Calculation** Logical effort (g) = (Input capacitance of gate / Input capacitance of inverter) × (Resistance of inverter / Resistance of gate) But for falling output, we only care about the pull-down path: \[ g = \frac{\text{Input capacitance seen by input "a"}}{\text{Input capacitance of inverter NMOS}} \times \frac{\text{Resistance of inverter NMOS}}{\text{Resistance of pull-down for input "a"}} \] - **Input capacitance:** Each NMOS has width 3, so input "a" sees 3 (from the upper NMOS) + 3 (from the lower NMOS) = **6 units**. - **Reference inverter NMOS input capacitance:** **1 unit** (width 1). - **Resistance of inverter NMOS:** **R**. - **Resistance of gate pull-down for input "a":** **2R/3**. \[ g = \frac{6}{1} \times \frac{R}{\frac{2R}{3}} = 6 \times \frac{3}{2} = 9 \] But this is for both transistors together, but the logical effort for a **single input** is: - For input "a", it controls **both NMOS** (series), but the input capacitance is **3** (for the NMOS it drives). - So: \[ g = \frac{3}{1} \times \frac{R}{\frac{2R}{3}} = 3 \times \frac{3}{2} = \frac{9}{2} = 4.5 \] But this is not matching the options. Let's look at the standard logical effort for a **2-input NAND**: - For a 2-input NAND, the logical effort per input is **4/3**. #### **Answer for 21:** The closest answer is **C. 4/3**. --- ### **Question 22** The schematic shows a **pull-up PMOS** network and a **single pull-down NMOS** network tied directly to ground (without a complementary NMOS). This configuration is typical of a **pseudo-NMOS** gate. #### **Answer for 22:** The answer is **C. pseudo-NMOS**. --- ## **Summary of Answers** 21. **C. 4/3** 22. **C. pseudo-NMOS**